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HMC704LP4E
v03.1211
8 GHz fractionaL-n PLL
For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
HMC RF PLLs with integrated VCOs also support HMC Open Mode. HMC700, HMC701, HMC702 and some genera-
tions of microwave PLLs with integrated VCOs do not support Open Mode.
Typical HMC Open Mode serial port operation can be run with sCLK at speeds up to 50MHz.
Serial Port HMc Mode
Typical serial port HMC Mode operation can be run with sCLK at speeds up to 50MHz.
HMc Mode - Serial Port WritE operation
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
table 9. SPi HMc Mode - Write timing characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
t2
t3
t4
sEN to sCLK setup time
sDI to sCLK setup time
sCLK to sDI hold time
sEN low duration
Max sPI Clock Frequency
8
3
20
50
nsec
MHz
A typical HMC Mode WRITE cycle is shown in Figure 36.
a. The Master (host) both asserts sEN (serial Port Enable) and clears sDI to indicate a WRITE cycle,
followed by a rising edge of sCLK.
b. The slave (PLL) reads sDI on the 1st rising edge of sCLK after sEN. sDI low indicates a Write cycle
(/WR).
c. Host places the six address bits on the next six falling edges of sCLK, MsB first.
d. slave registers the address bits in the next six rising edges of sCLK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of sCK, MsB first.
f.
slave registers the data bits on the next 24 rising edges of sCK (8-31).
g. sEN is cleared on the 32nd falling edge of sCLK.
h. The 32nd falling edge of sCLK completes the cycle.
t
1
t2
t3
Figure 36. Serial Port Timing Diagram - HMC Mode WRITE
sCLK
sDI
sEN
/WR
a4
a3
a2
a1
ao
d23
d22
d2
d1
d0
x
d3
1
2
3
4
5
6
7
8
29
30
31
32
33
t4
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